The present invention relates to system logic semiconductor chips for providing external support circuitry to implement a computer system with a microprocessor.
A microprocessor-based computer system would typically have a microprocessor directly coupled to a local bus, with dynamic random access memory (DRAM) coupled to the local bus. The control of memory read and write cycles to the DRAM is typically controlled by an external DRAM controller chip coupled to the local bus which provides the necessary timing and refresh signals for the DRAM, and decodes addresses to provide chip select signals to the appropriate bank of DRAM. One such DRAM controller is part no. 82C212, available from Chips and Technologies, Inc. in San Jose, Calif.
An I/O bus controller is typically coupled to the local bus for providing access to peripheral devices and add-on memory through a system bus, such as the IBM AT bus. The microprocessor is only coupled to the AT bus through the I/O bus controller.
A typical I/O bus controller will generate I/O bus cycle timing signals for every read and write cycle on the assumption that the device being read or written to is on the AT bus. The DRAM controller will determine whether a read or write cycle is for the local DRAM, and, if so, will produce an inhibit signal to the I/O bus controller and will provide its own timing signals on the local bus.
The I/O bus controller produces cycles which take much longer than the DRAM controller. A peripheral device which can operate faster than the normal I/O cycle can produce a zero wait state signal to the I/O bus controller indicating that the I/O cycles can be terminated early.
It is a continuing objective in the semiconductor industry to place more and more functions on a single chip to bring down the costs of personal computers. One of the limitations on such an effort in circuits with multiple buses such as discussed above is the limited number of input and output pins to a semiconductor chip. The packaging required for a chip with a very large number of pins becomes very expensive, and offsets the reduction in costs achieved through the use of a single chip.